Towards the end of last month, ARM Holdings announced two new CPU cores – the ARM Cortex-A75 (high-performance) and Cortex-A55 (high-efficiency) based on the ARM DynamIQ processor technology; and also a new GPU – the Mali-G72.
Built with Artificial Intelligence (AI) and machine learning (ML) applications in mind, the new processor’s (Cortex-A75 and Cortex-A55) DynamIQ multi-core technology was premiered back in March and promises to boost AI performance by over 50% in the next 3 – 5 years.
ARM Cortex-A75
The ARM Cortex-A75 offers a significant increase in performance and is targeted across a wide selection of markets, from edge to the cloud. It can either be used standalone with up to 4 high-performance processors, or in big.LITTLE combination with the Cortex-A55 processor, with up to 8 processors in total.
When compared to its predecessor – the Cortex-A73, here are some of the highlights:
- > 20% more mobile performance vs Cortex A73.
- Same sustained performance as Cortex-A73.
- +40% improved performance in infrastructure.
ARM Cortex-A55
The ARM Cortex-A55, successor to 2012’s Cortex-A53, implements the latest ARMv8.2 architecture, and promises improced performance, reduced power use and advanced features for future applications.
Compared to the A53, the A55 has:
- Up to 2x more memory performance than Cortex-A53 at iso-frequency, iso-process
- Up to 15% better power efficiency than Cortex-A53 at iso-frequency, iso-process
- More than 10x more scalability than Cortex-A53
ARM Mali-G72
The ARM Mali G72 with improved bifrost architecture builds on the success of the Mali-G71 (up tp 40% increase in performance). It is designed for High Fidelity Mobile Gaming and the emerging field of Machine Learning (ML) on device.
Below are some of the highlights:
- 1.4x expected in-device performance when compared to 2017 devices
- 25% higher energy efficiency and 20% better area efficiency
- 17% increase in machine learning efficiency
- Multiple Bifrost optimizations including increased tile buffer memory, tiler scalability and L1 caches sizes
Source: ARM Community